Abstract
The delayed least-mean-square (DLMS) algorithm is useful for adaptive finite impulse response (FIR) filtering applications where high throughput rates are required. In this paper, a bit-serial bit-level systolic array based on a new scheme for multiplication and inner product computation is presented to implement DLMS adaptive N-tap FIR filters. The architecture is highly regular, modular, and thus well suited to VLSI implementation. It has an efficiency of 100 percent and a throughput rate of one filter output per 2B cycles, where B is the word length of input data. In addition, the proposed array uses a small delay of [(4B+N/2+4)/2B] in the filter coefficient adaptation, where [x] is the smallest integer greater than or equal to x. This ensures that the DLMS algorithm can have good performance under proper selection of the step size. Due to the use of bit-serial arithmetic, the proposed system can be realized in a single chip for most practical applications.