Abstract
Analog-to-time conversion has been one alternative method of converting continuous-valued, biomedical signals into pulse-width-modulated (PWM) digital signals for reliable data transmission and signal processing. As most data classification algorithms rely on inner product with feature vectors, this paper presents a compact architecture for performing multiplication and accumulation on PWM signals. The proposed architecture contains a dual-scale counter (DSC) and a two-dimensional multiply-accumulate (2D-MAC) operator. The DSC converts a time-mode (PWM) signal to digital data containing one coarse-count value and one fine-count value. The 2D-MAC then performs a multiply-accumulate (MAC) operation based on the coarse-count and fine-count values. The full architecture has been realized in a field-programmable gate array (FPGA) for demonstration. A comparison of the proposed 2D-MAC operator with an 8 bit resolution MAC operator from the FPGA intellectual property library is also presented. Experimental results reveal that the 2D-MAC with DSC operator can reduce the chip area, while consumes compatible power with the FPGA IP library.