Abstract
Fault-based verification technique is a method to qualify a verification environment. The better verification environment can detect output differences between the fault-free and fault-injected circuits with a higher probability. Since different injected faults could cause the same output response under all stimuli, which are called equivalent faults, maximally identifying these equivalent faults can improve the efficiency of verification environment qualification without sacrificing its quality. The 2016 CAD Contest at ICCAD posed the problem of identifying equivalent faults in the circuits. This paper presents our work in the Contest with some improvements.