Abstract
A phase-locked loop (PLL), in which the ripple in the control voltage is suppressed to minimize the output phase jitter, is proposed. A discriminator-aided edge detector is added in the PLL to switch the outputs of the loop filter to reduce the ripple. The proposed PLL and the conventional circuit have been implemented in a 0.35-μm CMOS process. Compared with the conventional PLL, the rms jitter is reduced from 19.0 ps to 18.3 ps and the peak-to-peak jitter is reduced from 148.2 ps to 139.1 ps. © 2006 IEEE.