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A multi-ESD-path low-noise amplifier with a 4.3-A TLP current level in 65-nm CMOS
Conference paper   Peer reviewed

A multi-ESD-path low-noise amplifier with a 4.3-A TLP current level in 65-nm CMOS

Ming-Hsien Tsai, Shawn S. H. Hsu, Fu-Lung Hsueh and Chewn-Pu Jou
IEEE Transactions on Microwave Theory and Techniques, Vol.58(12 PART 2), pp.4004-4011
12/2010

Abstract

CMOS electrostatic discharge (ESD) low-noise amplifier (LNA) radio frequency (RF) silicon-controlled rectifier (SCR) transmission-line pulse (TLP)
This paper studies the electrostatic discharge (ESD)-protected RF low-noise amplifiers (LNAs) in 65-nm CMOS technology. Three different ESD designs, including double-diode, modified silicon-controlled rectifier (SCR), and modified-SCR with double-diode configurations, are employed to realize ESD-protected LNAs at 5.8 GHz. By using the modified-SCR in conjunction with double-diode, a 5.8-GHz LNA with multiple ESD current paths demonstrates a 4.3-A transmission line pulse (TLP) failure level, corresponding to a ∼ 6.5-kV Human-Body-Mode (HBM) ESD protection level. Under a supply voltage of 1.2 V and a drain current of 6.5 mA, the proposed ESD-protected LNA demonstrates a noise figure of 2.57 dB with an associated power gain of 16.7 dB. The input third-order intercept point (IIP3) is -11 dBm, the input and output return losses are greater than 15.9 and 20 dB, respectively. © 2006 IEEE.

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