Abstract
The emergence of 3D-stacking in semiconductor technology has revolutionized CIS chip design, offering enhanced performance and efficiency in a smaller form factor. Pulse-width modulation (PWM) pixels are favored for stacking due to the time-domain output with immunity to interconnection impedance and downstream noise. Recent research simplified comparator designs, enabling the integration of all pixel devices into stacked chips. However, in the latest 3-layer wafer stacking processes, the intermediate layer can only accommodate NMOS design, posing a challenge for achieving an NMOS-only PWM pixel circuit. Current research on PWM pixel circuits mainly focuses on two types of architecture. The first type, proposed in [1–2], employs a common source as the in-pixel comparator, enabling a high-gain output at low voltages, however, requiring the use of PMOS. Moreover, the voltage gain, which depends on the input signal, may affect the circuit linearity. The second type, proposed in [3–5], uses NMOS as a switch, benefiting from using only NMOS components. However, the conductivity of an NMOS switch also depends on the threshold voltage and body effect, leading to signal-dependent variations which impact the overall linearity. Thus, mitigating the body effect is crucial for achieving high linearity. In this work, in-pixel voltage-to-time conversion is achieved by using only three NMOS devices, while the influence of body effect on the linear response is addressed through the proposed differential comparison technique.