A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI

Chih-Wen Lu; Chung Len Lee; Jwu E. Chen; Chauchin Su

doi:10.1109/IDDQ.1998.730757

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Conference paper

A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI

Chih-Wen Lu, Chung Len Lee, Jwu E. Chen and Chauchin Su

Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998, Vol.1998-November, 730757

1998

DOI: https://doi.org/10.1109/IDDQ.1998.730757

Abstract

Computer Networks and Communications

Electronic

Optical and Magnetic Materials

Electrical and Electronic Engineering

Hardware and Architecture

In this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability.

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Title: A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI
Creators - without role: Chih-Wen Lu - Department of Electronics Engineering , National Chiao Tung University
Chung Len Lee - National Yang Ming Chiao Tung University
Jwu E. Chen - Chung Hua University
Chauchin Su - National Central University
Identifiers: 0818691913; 9780818691911; 9957775240806774
Academic Unit: Department of Engineering and System Science, College of Nuclear Science, National Tsing Hua University
Language: English
Resource Type: Conference paper
Publication Details: Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998, Vol.1998-November, 730757

A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI

Abstract

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