Abstract
This paper presents the design of a nonlinear wireless power transfer receiver. In the proposed receiver, a switch is introduced to control the quality factor of the impedance at the power receiving interface. The effective impedance can then be adjusted by jointly varying the switching timing and DC loading to deliver the required power while improving the conversion efficiency at the same time. Designed with a 0.25-μm HV CMOS process and an operating frequency of 6.78 MHz, simulation results show that an output power of more than 2.8 W can be obtained with coupling coefficient varying from 0.05 to 0.26 with a maximum output power of 5.64 W, and the maximum power conversion efficiency is 80.2%.