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A novel 3D IC assembly process for ultra-thin chip stacking
Conference paper

A novel 3D IC assembly process for ultra-thin chip stacking

Yu-Min Lin, Chau-Jie Zhan, Zhi-Cheng Hsiao, Huan-Chun Fu, Ren-Shin Cheng, Yu-Wei Huang, Shin-Yi Huang, Su-Mei Chen, Chia-Wen Fan, Chun-Hsien Chien, …
2014 International Conference on Electronics Packaging, ICEP 2014, pp.470-474
2014

Abstract

Chip-on-wafer (CoW) Chip-stacking Sheet molding compound (SMC) Wafer-level-packaging (WLP) Electronic Optical and Magnetic Materials
A novel assembly process was developed for ultra-thin chip stacking technology where wafer-level-packaging (WLP) was adopted and combined with chip-on-wafer (CoW) technology. By such assembly process, thin chip handling would be unnecessary in this process. After assembly process, chip thickness within the chip stack could be thinned down to a thickness of 30μm or less than 30μm. Sheet-type molding compound (SMC) was used to achieve the assembly of ultra-thin chip stacking module. The feasibility of this novel assembly was demonstrated and some process issues were also discussed in this investigation.

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