Abstract
The Ron sp of a DMOS operated at high side (Ron-sp-HS) in the power management ICs is usually underestimated by taking the measured value at low side operation (Ron-sp-LS). The Ron-sp-HS is increased drastically when a revise voltage is applied between drift region and substrate because the drift-region is depleted and the current path is narrowed. In this paper, a novel structure with a varying-junction-depth profile in the drift region is proposed to suppress the increase of Ron-sp-HS by adding a partial n-type buried layer (NBL) under the drain region. The drift region of HS-DMOS will generate a gradual pinch-off region from channel to drain when it is operated at 80V under high side operations, and the increased percentage in Ron-sp-HS is suppressed from 128% to 79% because it allows a wider electron current flow through the neutral region of the drift region in the proposed structure.