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A novel logarithmic response CMOS image sensor with high output voltage swing and in-pixel fixed pattern noise reduction
Conference paper

A novel logarithmic response CMOS image sensor with high output voltage swing and in-pixel fixed pattern noise reduction

Liang-Wei Lai and Ya-Chin King
2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, pp.105-108
2002
DOI: https://doi.org/10.1109/APASIC.2002.1031543

Abstract

CMOS image sensor lateral PNP logarithmic response Hardware and Architecture Electrical and Electronic Engineering
A novel logarithmic response 0.25 μm CMOS image sensor technology for high output swing and low noise error is proposed. The experimental results show that the new cell has 4 times higher output voltage swing. Optimized simulation results show 6.5 times larger output voltage swing, which is achievable for an input signal range of 0.01 lux to 100,000 lux. With this wider swing, the effect of fixed pattern noise (FPN) reflecting on the digital output can be reduced significantly. In addition, after adding a correlated double sampling (CDS) control transistor, the output voltage difference variation due to FPN is greatly reduced from 73 mV to 15 mV.

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