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A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND flash EEPROM s
Conference paper

A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND flash EEPROM s

Masayuki Ichige, Yuji Takeuchi, Kikuko Sugimae, Atsuhiro Sato, Michiharu Matsui, Takeshi Kamigaichi, Hiroyuki Kutsukake, Yutaka Ishibashi, Masanobu Saito, Seiichi Mori, …
Digest of Technical Papers - Symposium on VLSI Technology, pp.89-90
2003

Abstract

Electrical and Electronic Engineering
A new self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND flash EEPROMs was discussed. Shallow trench isolation (STI) which is used to reduce memory cell size was also studied. It was found that this technology can be applied to 2 Gbit binary and 4 Gbit multi level memory cells.

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