A novel single poly-silicon EEROM using trench floating gate

Meng-Yi Wu; Shin-Chang Feng; Ya-Chin King

doi:10.1109/MTDT.2005.13

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Conference paper

A novel single poly-silicon EEROM using trench floating gate

Meng-Yi Wu, Shin-Chang Feng and Ya-Chin King

Records of the IEEE International Workshop on Memory Technology, Design and Testing, pp.35-37

2005

DOI: https://doi.org/10.1109/MTDT.2005.13

Abstract

A novel Single Poly-silicon Trench Gate-type EEPROM, SPTG, featuring low voltage operation and fast programming is proposed. Using a trench floating gate instead of the stack gate structure, this cell is suitable for embedded application. The trenched floating gate (FG) combining with a deep-N-well implanted region guarantees high coupling ratio for CHEI programming and source side FN erasing operation. This cell array in a NOR-type array features fast random access capacity and 11F ² cell size. © 2005 IEEE.

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Title: A novel single poly-silicon EEROM using trench floating gate
Creators - without role: Meng-Yi Wu - National Tsing Hua University
Shin-Chang Feng - National Tsing Hua University
Ya-Chin King - National Tsing Hua University
Publication Details: Records of the IEEE International Workshop on Memory Technology, Design and Testing, pp.35-37
Grant note: IEEE Computer Society Test Technology Technical Co
Identifiers: 0769523137; 9957770596106774
Academic Unit: Institute of Electronics Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

A novel single poly-silicon EEROM using trench floating gate

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