Abstract
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been proposed for high-performance integrated circuits. In this paper, we present a performance-driven multilevel framework for the X-based full-chip router. To fully consider performance-driven routing and take advantage of the X-architecture, we apply a novel multilevel routing framework, which adopts a four-stage technique of a trial routing stage, followed by a top-down uncoarsening stage, with an intermediate track routing stage, and then followed by a bottom-up coarsening stage. Compared with the state-of-the-art work, we achieve 100% routing completion for all circuits while reduced the net delay. © 2009 Springer Berlin Heidelberg.