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A sizing methodology for a low-noise comparator
Conference paper

A sizing methodology for a low-noise comparator

Kuo-Hsin Lai, Shi-Yu Huang and Pei-Chia Chiang
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Vol.1, pp.253-256
2004

Abstract

We present a methodology to reduce the charge injection noise for an offset-free comparator, so as to achieve a higher resolution. Our method incorporates an algorithm that automatically searches for the optimal transistor sizes in the comparator. The values of this methodology are in two aspects. First, it takes away from designers the burden of sizing the transistors. Second, it is fully automatic and could ease the technology migration process. Experimental results show that the resolution can be improved by an order of magnitude through this methodology. © 2004 IEEE.

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