- Title
- A systematic approach to semiconductor memory test time reduction
- Creators - without role
- S.-H. ShiehC.-W. Wu - 國立清華大學電機資訊學院電機工程學系
- Publication Details
- Proc. 15th VLSI Design/CAD Symp.
- Identifiers
- 9957772284406774
- Academic Unit
- College of Electrical Engineering and Computer Science, National Tsing Hua University
- Language
- Traditional Chinese
- Resource Type
- Conference paper
Conference paper
A systematic approach to semiconductor memory test time reduction
Proc. 15th VLSI Design/CAD Symp.
2004
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