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A systolic RSA public key cryptosystem
Conference paper

A systolic RSA public key cryptosystem

P.-S. Chen, C.-W. Wu and S.-A. Hwang
1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96, pp.408-411
05/1996

Abstract

Public key cryptography;Systolic arrays;Very large scale integration;Clocks,Public key;Algorithm design and analysis;Prototypes;Security;Added delay;Iterative algorithms Computer Science
A bit-level systolic array for RSA public key cryptosystem is designed based on our modified Montgomery's algorithm. Since the post adjustment in the original algorithm is removed, the modified algorithm leads to both simpler architecture and better performance, A prototype CMOS VLSI chip was designed and simulated, which implements a 512-bit RSA cryptosystem. This chip can achieve an encryption (or decryption) rate of 24.3 Kb/sec under a 50 MHz clock.

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