Abstract
This paper presents a new parallel-in-parallel-out bit-level systolic array with unidirectional data flow for computing exponentiation in GF(2 m ). The array is highly regular, modular, and thus well suited to VLSI implementation. In addition, It can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. As compared to a previously known systolic GF(2 m ) exponentiator with the same throughput performance, the proposed system requires much less amount of chip area, has smaller latency, and is easier to incorporate fault-tolerant design.