A test structure to verify the robustness of silicided N+/P+ interface

Cheng-Yao Lo; Shyue-Shyh Lin; Wei-Ming Chen; Yuh-Jier Mii

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A test structure to verify the robustness of silicided N+/P+ interface

Cheng-Yao Lo, Shyue-Shyh Lin, Wei-Ming Chen and Yuh-Jier Mii

IEEE International Conference on Microelectronic Test Structures, pp.169-172

2004

Abstract

We propose a new test structure that provides a single current path for suicide robustness detection at N+/P+ butted well tap interface with good sensitivity. Two reference test structures suspected with more than one current path and consequently give false results are also compared for structure and electrical performances.

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Title: A test structure to verify the robustness of silicided N+/P+ interface
Creators - without role: Cheng-Yao Lo - Advanced Logic-1 , Logic Technology Division , Taiwan Semiconduct. Mfg. Co., Ltd.
Shyue-Shyh Lin - Advanced Logic-1 , Logic Technology Division , Taiwan Semiconduct. Mfg. Co., Ltd.
Wei-Ming Chen - Advanced Logic-1 , Logic Technology Division , Taiwan Semiconduct. Mfg. Co., Ltd.
Yuh-Jier Mii - Advanced Logic-1 , Logic Technology Division , Taiwan Semiconduct. Mfg. Co., Ltd.
Publication Details: IEEE International Conference on Microelectronic Test Structures, pp.169-172
Identifiers: 9957767447706774
Academic Unit: Institute of NanoEngineering and Microsystems, College of Engineering, National Tsing Hua University
Language: English
Resource Type: Conference paper

A test structure to verify the robustness of silicided N+/P+ interface

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