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A unified method for parametric fault characterization of post-bond TSVs
Conference paper

A unified method for parametric fault characterization of post-bond TSVs

Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng and Stephen Sunter
Proceedings - International Test Conference, 6401566
2012

Abstract

3D IC Characterization Design for Testability Leakage Fault Parametric Fault Resistive Open Fault Through-Silicon Via
A TSV in a 3D IC could suffer from two major types of parametric faults - a resistive open fault, or a leakage fault. Dealing with these parametric faults (which do not destroy the functionality of a TSV completely but only degrade its quality or performance) is often trickier than dealing with a stuck-at fault. Previous works have not proposed a unified test structure and method that can characterize their respective effects. Based on our previous test structure, called VOT (Variable Output Threshold) scheme for delay faults, we propose a unified in-situ characterization flow for both parametric fault types of a post-bond TSV. With this flow, one can easily derive a more insightful assessment of a parametric fault in production test, process monitoring, and/or diagnosis-driven yield learning. © 2012 IEEE.

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