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A word-based RSA crypto-processor with enhanced pipeline performance
Conference paper

A word-based RSA crypto-processor with enhanced pipeline performance

Chen-Hsing Wang, Chih-Pin Su, Chih-Tsun Huang and Cheng-Wen Wu
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp.218-221
2004

Abstract

Engineering (all)
We propose a high speed RSA crypto-processor based on an enhanced word-based Montgomery Multiplication (MM) algorithm. With the help of the proposed Correction Module (CM), the word-based modular multiplier can achieve 100% utilization. A simplified Parity Trediction Module (PPM) is also proposed to eliminate the pipeline stall. Using a 0.18μm CMOS standard cell library, our RSA crypto-processor achieves a 512-bit RSA encryption rate of 3/5Kbps under 300MHz clock. The result shows that our architecture is cost-effective in terms of area and performance.

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