摘要
Critical systems require extensive simulation effort with functional fault injection on RTL circuits during design stages in order to analyze vulnerability and engineer error-tolerant measures accordingly. Yet for a complex SoC, long simulation cycles are necessary for each injected fault. Therefore it is imperative to prune as many faults as possible to improve simulation efficiency and turn-around time for designers.In this paper, we propose a novel method (ACE-Pro) to reduce the functional fault list. The method extends architecturally correct execution (ACE) analysis by creating a propagation graph, where a node is a fault marked with an ACE bit at a cycle and a directed link between nodes represents the propagation condition to another register at the next cycle. By checking and propagating through the graph the properties of masking (a fault is masked by logic on its propagation path to next registers) and singly-equivalence (a fault is covered by another fault on the next register), we show fault reductions by 98.91% to 99.91% (49.2% to 88.4% from the reduced faults in Equivalent Regions) in our experiments on a RISC-V core.