Abstract
Since most DSP applications access large amount of data stored in the memory, a DSP code generator must minimize the addressing overhead. In this paper, we propose a method for addressing optimization in loop execution targeted toward DSP processors with autoincrement/ decrement feature in their address generation unit. Our optimization methods include a multi-phase data ordering and a graph-based address register allocation. The proposed approachelr have been evaluated using a set of core algorithms targeted towards the TI TMSSZOC40 DSP proceaaor. Experimental results show that our system is indeed more effective compared to a commercial optimizing DSP compiler.