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An 8-bit column-shared SAR ADC for CMOS image sensor applications
Conference paper

An 8-bit column-shared SAR ADC for CMOS image sensor applications

Jin-Yi Lin, Kwuang-Han Chang, Chen-Che Kao, Shih-Chin Lo, Yan-Jiun Chen, Pei-Chen Lee, Chi-Hui Chen, Chin Yin and Chih-Cheng Hsieh
Proceedings - IEEE International Symposium on Circuits and Systems, Vol.2015-July, pp.301-304
27/07/2015
DOI: https://doi.org/10.1109/ISCAS.2015.7168630

Abstract

CMOS image sensors (CIS) Low power successive approximation analog-to-digital converter (SAR ADC)
This paper presents an 8-bit asynchronous SAR ADC for CMOS image sensor applications in 130nm 1P4M technology. The proposed one-side merge-and-split switching effectively reduces the DAC switching energy because the reference voltage is halved. In addition, considering the bottom-plate parasitic capacitance, the proposed method can have better power efficiency compared to other methods. With 1.5V supply and Nyquist rate input, the prototype consumes 330μW at 16MS/s and achieves an ENOB of 7.21bit and a SFDR of 62.77dB, respectively. The resultant FoM is 139fJ/conv-step. © 2015 IEEE.

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