An AVPG for SOC design verification with port order fault model

C.-Y. Wang; S.-W. Tung; J.-Y. Jou

Back

Conference paper

An AVPG for SOC design verification with port order fault model

C.-Y. Wang, S.-W. Tung and J.-Y. Jou

Proceedings - IEEE International Symposium on Circuits and Systems, Vol.5, pp.259-262

2001

Abstract

Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because the high complexity of SoC, the design verification is a challenge for system integrator. To reduce the verification complexity, the port order fault (POF) model has been used for verifying the core-based design. In this paper, we present a verification scheme and an automatic verification pattern generation (AVPG) system based on POF model.

Metrics

1 Record Views

Details

Title: An AVPG for SOC design verification with port order fault model
Creators - without role: C.-Y. Wang - Dept. of Electronics Engineering , National Chiao Tung University
S.-W. Tung - Dept. of Electronics Engineering , National Chiao Tung University
J.-Y. Jou - Dept. of Electronics Engineering , National Chiao Tung University
Publication Details: Proceedings - IEEE International Symposium on Circuits and Systems, Vol.5, pp.259-262
Grant note: IEEE
Identifiers: 9957767175306774
Academic Unit: Department of Computer Science, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

An AVPG for SOC design verification with port order fault model

Abstract

Related links

Metrics

Details

National Tsing Hua University Social media