摘要
In advanced technology nodes, it is becoming common to mix standard cells with different heights in the same design to optimize timing, power, and routability simultaneously. In this paper, we explore the placement problem of mixed-cell-height designs that include half-row-extended (HRE) cells and conventional single-row-height cells. An HRE cell is like a conventional single-row-height cell extended by half a row both upward and downward, resulting in a double-row-height cell. The advantage of an HRE cell is its superior driving strength compared to a conventional double-row-height cell, where both the top and bottom cell boundaries are aligned with power or ground rails. But mixing HRE cells with conventional single-row height cells may result in a less compact placement, which adversely affects the wirelength and/or the chip size. To address the placement challenges introduced by HRE cells, we propose a two-level placement framework: (1) HRE cell-aware global placement and (2) half-row-fragment-aware legalization. During the global placement, we estimate the potential area overhead caused by the HRE cells and identify groups of HRE cells that should be placed close to one another to control the whitespace distribution while minimizing the wirelength. Then, we invoke FragmentSaver, a legalizer that leverages deadspace cost curves to reduce row fragmentation with minimal displacement. Experimental results show that, compared to the state-of-the-art mixed-cell-height placer RePIAce [8], our method resulted in significant reductions in routed wirelength and cell displacement.