An FPGA fault simulator for stuck-at and segment delay faults

Conference paper

An FPGA fault simulator for stuck-at and segment delay faults

H.-C. Liao, R.-F. Huang, J.-J. Liou and C.-W. Wu

Proc. 14th VLSI Design/CAD Symp., pp.461-464

2003

Abstract

FPGA;simulator

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Title: An FPGA fault simulator for stuck-at and segment delay faults
Creators - without role: H.-C. Liao
R.-F. Huang
J.-J. Liou
C.-W. Wu - 國立清華大學電機資訊學院電機工程學系
Identifiers: 9957771815806774
Academic Unit: College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: Traditional Chinese
Resource Type: Conference paper
Publication Details: Proc. 14th VLSI Design/CAD Symp., pp.461-464