An adaptive-rate error correction scheme for NAND flash memory

Te-Hsuan Chen; Yu-Ying Hsiao; Yu-Tsao Hsing; Cheng-Wen Wu

doi:10.1109/VTS.2009.24

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Conference paper

An adaptive-rate error correction scheme for NAND flash memory

Te-Hsuan Chen, Yu-Ying Hsiao, Yu-Tsao Hsing and Cheng-Wen Wu

Proceedings of the IEEE VLSI Test Symposium, pp.53-58

2009

DOI: https://doi.org/10.1109/VTS.2009.24

Abstract

BCH code

Error correction

Flash memory

Memory fault tolerance

Memory management

Computer Science Applications

Electrical and Electronic Engineering

ECC has been widely used to enhance flash memory endurance and reliability. In this work, we propose an adaptive-rate ECC scheme with BCH codes that is implemented on the flash memory controller. With this scheme, flash memory can trade storage space for higher error correction capability to keep it usable even when there is a high noise level. © 2009 IEEE.

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Title: An adaptive-rate error correction scheme for NAND flash memory
Translated title: An adaptive-rate error correction scheme for NAND flash memory
Creators - without role: Te-Hsuan Chen - National Tsing Hua University
Yu-Ying Hsiao - National Tsing Hua University
Yu-Tsao Hsing - National Tsing Hua University
Cheng-Wen Wu - Department of Electrical Engineering , National Tsing Hua University
Identifiers: 9780769535982; 9957776834306774
Academic Unit: College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper
Publication Details: Proceedings of the IEEE VLSI Test Symposium, pp.53-58

An adaptive-rate error correction scheme for NAND flash memory

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