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An application-independent delay testing methodology for Island-style FPGA
Conference paper

An application-independent delay testing methodology for Island-style FPGA

Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang and Cheng-Wen Wu
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.478-486
2004
DOI: https://doi.org/10.1109/DFTVS.2004.1347873

Abstract

Delay testing FPGA Path delay fault Segment delay fault Engineering (all)
A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our fault model assumes that a target segment can be covered by a shortest path which is realizable in an FPGA. And the path will guarantee to detect delay defects which affect the performance of the segment. Given the proposed fault model, we also developed a framework to search for the target paths and find appropriate tests, which is independent to the size of FPGAs. Several methods are also proposed to minimize the number of test configurations (the test time). The tests can achieve a high coverage of delay defects with reasonable test time. © 2004 IEEE.

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