Abstract
Increasing the operation speed is the possible way to realize a monolithic switching converter with on-chip LC filter. However the performance of output ripple, power efficiency, and operation range are relative to the technology, area occupation, and circuit topology. In this work, with a 0.18-m CMOS, the hysteresis-based control regulates the converter at 100 MHz switching frequency for the balance of filter size and power efficiency. The feedforward ripple cancellation technique reduces the output ripple further diminish the LC filter. To ease the design complexity, we build up a design flow started from the area limitation to help each circuit parameter decision. All these techniques have been proven in a fully integrated DC-DC converter prototype, although this shuttle suffers from worse process shift. The active area is about 3 mm 2 . The input is 3.3 V and the regulated output is 1.8 V with less than 5.5% (1.1% in post-sim) ripple. The maximum power efficiency is 48.3% (52.5% in post-sim) under 20mA to 90mA loading current. © 2012 IEEE.