Abstract
Decreasing read cell current (I CELL ) has become a key trend in nonvolatile memory (NVM). This is not only due to device size and V DD scaling while keeping the same threshold voltage (V TH ), but also to the growing spread of the following applications: 1) multiple-level-cell (MLC) [1-2] to achieve smaller area-per-bit; 2) lower-V DD [3] to save power consumption; 3) Logic-process-compatible onetime programming memories (OTP) for embedding into mobile chips. A smaller I CELL leaves the sense amplifiers (SAs) operation vulnerable to 1) bitline (BL) level offset due to noise, bias and load (C BL ) mismatches and 2) V TH variation. As device size and BL-pitch is continually scaled down, the above factors have become major showstopper for SAs. To tolerate these offsets, small-I CELL NVMs suffer from slow read speed or high read fail probability. Thus, a more largely offset tolerant SA is a prerequisite to achieve faster read speeds. In this study, we propose a new offset tolerant current-sampling-based SA (CSB-SA) to achieve 7x faster read speed than previous SAs for sensing small I CELL . A fabricated 90nm 512Kb OTP macro, using the CSB-SA and our CMOS-logic-compatible OTP cell [4], achieves 26ns macro random access time for reading sub-200nA I CELL . Measurements also confirmed that this 90nm CSB-SA could achieve sub-100nA sensing. © 2011 IEEE.