An on-chip learning, low-power probabilistic spiking neural network with long-term memory

Hung-Yi Hsieh; Kea-Tiong Tang

doi:10.1109/BioCAS.2013.6679626

Back

Conference paper

An on-chip learning, low-power probabilistic spiking neural network with long-term memory

Hung-Yi Hsieh and Kea-Tiong Tang

2013 IEEE Biomedical Circuits and Systems Conference, BioCAS 2013, pp.5-8

2013

DOI: https://doi.org/10.1109/BioCAS.2013.6679626

Abstract

This paper describes an analog probabilistic spiking neural network (PSNN) circuit for portable and implanted applications which especially require low power, small area and on-chip learning to ensure good mobility, body safety and continually accurate classification. The circuit is implemented using TSMC 0.18μm CMOS technology. Simulation results show that the circuit can learn linearly non-separable exclusive-or (xor) problem under 1V supply with only 3.8μW of power consumption. Long-term, multi-stage synaptic memory contains more information for a longer time in a single synapse. Comparison of the proposed PSNN with recent hardware neural networks is also provided. © 2013 IEEE.

Metrics

1 Record Views

Details

Title: An on-chip learning, low-power probabilistic spiking neural network with long-term memory
Creators - without role: Hung-Yi Hsieh - National Tsing Hua University
Kea-Tiong Tang - Department of Electrical Engineering , National Tsing Hua University
Publication Details: 2013 IEEE Biomedical Circuits and Systems Conference, BioCAS 2013, pp.5-8
Identifiers: 9781479914715; 9957773157406774
Academic Unit: Department of Electrical Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

An on-chip learning, low-power probabilistic spiking neural network with long-term memory

Abstract

Related links

Metrics

Details

National Tsing Hua University Social media