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An ultra-low power K-band low-noise amplifier co-designed with ESD protection in 40-nm CMOS
Conference paper

An ultra-low power K-band low-noise amplifier co-designed with ESD protection in 40-nm CMOS

Ming-Hsien Tsai, Shawn S.H. Hsu, Fu-Lung Hsueh, Chewn-Pu Jou, Tzu-Jin Yeh, Ming-Hsiang Song and Jen-Chou Tseng
2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011, 5783220
2011

Abstract

Electrostatic discharge (ESD) Low-noise amplifier (LNA) Radio frequency (RF) Shallow-trench isolation (STI) Hardware and Architecture Electrical and Electronic Engineering
This paper presents a K-band low noise amplifier (LNA) co-designed with ESD protection circuit in 40-nm CMOS technology. By treating ESD devices as a part of the input matching network, an ESD protected 24-GHz LNA is demonstrated with a NF of 3.2 dB under a power consumption of only 4.1 mW. The ESD protection network is composed of dual-diode and a gate-driven power clamp achieving an ESD level of 2.8 kV human body model (HBM). Owing to the co-design approach, the NF only degrades by 0.2 dB compared with the reference LNA without the ESD network. The ESD-LNA presents a power gain of 13.0 dB with the input and output return losses both greater than 10 dB. To the best of our knowledge, this is the first report on a 24-GHz ESD-protected LNA in 40-nm CMOS. © 2011 IEEE.

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