Abstract
The power dissipation is the concern for SoC de-signs and embedded systems to extend battery life. Techniques like dynamic voltage scaling (DVS), power gating (PG), and mul-tiple domain partitioning help provide mechanisms to reduce dy-namic and static powers. Based on those techniques, the control system can be system software or hardware monitors. In ether cases, energy estimations in the architecture level are needed to facilitate the design space explorations of architecture and soft-ware scheduling designs for energy reductions. In this paper, we propose an architecture-level simulation environment for secu-rity processors with power estimation. The simulation environ-ment includes a transaction-level modeling (TLM) simulator im-plemented in SystemC with multiple power domains, an analyti-cal model, a workload generator, power parameter banks, versa-tile outputs, and succinct GUIs. Architecture developers can use it to evaluate different architecture configurations and retrieve per-formance results and power estimations. System software devel-opers can use these tools for experiments in devising power-aware scheduling methods on security processors for power dissipation reduction.