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CACTI-FinFET: An integrated delay and power modeling framework for FinFET-based caches under process variations
Conference paper

CACTI-FinFET: An integrated delay and power modeling framework for FinFET-based caches under process variations

Chun-Yi Lee and Niraj K. Jha
Proceedings - Design Automation Conference, pp.866-871
2011
DOI: https://doi.org/10.1145/2024724.2024918

Abstract

cache simulator;CACTI-FinFET;FinFETs;process variation;integrated delay;power modeling framework Computer Science Applications,Control and Systems Engineering,Electrical and Electronic Engineering,Modeling and Simulation
We present CACTI-FinFET, an integrated framework for simulation of power, delay, temperature, as well as process variations of FinFET-based caches. We have developed a FinFET design library and process variation models to characterize the delay and leakage spreads of such caches. We present results for various FinFET design styles and show that mixing different design styles may be a promising strategy for optimizing cache delay and leakage. © 2011 ACM.

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