Abstract
The authors present stress distribution simulation characterization of the three-dimensional boundary effects and show how these effects can impact the achievable transistor performance gain. The high-performance complementary metal-oxide-semiconductor (CMOS) device has been achieved by stressors such as contact etch stop layer (CESL) and SiGe S/D and optimal geometric structure design. The biaxial-like stress distribution resulting from symmetry structure and uniaxial-like stress distribution resulting from asymmetry structure seems to be promising when considering drive current enhancement, the ballistic efficiency, and carrier injection velocity for CMOS devices. The comprehensive study helps the future nanoscale CMOS device design and demonstrates that the stress enhancement factors remain valid for future technology. © 2009 American Vacuum Society.