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Clipping Error Compensation for Accuracy Recovery and Throughput Improvement in Computing-in-Memory
會議論文

Clipping Error Compensation for Accuracy Recovery and Throughput Improvement in Computing-in-Memory

Yu-Chih Tsai, Hsuan-Hung Shen 和 Ren-Shuo Liu
IEEE International Symposium on Circuits and Systems proceedings, 頁碼.902-906
IEEE
2026 IEEE International Symposium on Circuits and Systems (ISCAS) (Shanghai, China, 24/05/2026–28/05/2026)
24/05/2026

摘要

accelerator Accuracy analog-to-digital converter built-in self-repair clipping error Common Information Model (computing) Common Information Model (electricity) Computer integrated manufacturing computing-in-memory Convolutional neural networks Hardware In-memory computing Information rates Modeling Printing
This paper proposes built-in self-repair (BISR) strategies for computing-in-memory (CIM) architectures to mitigate clipping errors in convolutional neural networks (CNNs) and enhance overall CIM performance.First, we propose a BISR circuit that detects and compensates clipping errors in real-time. When a bitline output of the CIM approaches the upper limit of the analog-to-digital converter (ADC), a pre-stored compensation value is added to preserve inference accuracy. Second, we observe a strong correlation between clipping errors and the sum-of-weight-bits on bitlines. Based on this, we introduce a grouping scheme that records compensation values by sum-of-weight-bits ranges, reducing storage overhead while maintaining accuracy.Experiments on image classification show the proposed BISR recovers the top-1 accuracy loss to approximately 1% and improves CIM throughput by up to 3.2×. The hardware incurs only about 5% additional area relative to the CIM macro, excluding ADCs and DACs.

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