Abstract
We propose a method for compiling an application program into microcodes of a programmable DSP processor. Since most state-of-the-art DSP processors feature some sort of parallel processing architectures, the code generation is a non-trivial task. Based on several scheduling and allocation techniques previously developed by the CAD community for high-level synthesis, we propose a DSP code generator. We emphasize on reducing the memory access and register usage conflicts, which often lengthen the total execution time. Starting with an as soon as possible scheduling without regarding to the resource constraints, we transform the scheduling step-by-step into a legal one. In the mean time, registers are allocated and re-allocated for variables taking into account both the memory access and register usage constraints. A software system called THEDA. DSP CG has been implemented and tested using a set of benchmark programs. Simulation of the generated codes targeted towards the TI TMS320C40 DSP processor shows that the proposed approach is indeed very effective.