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Compact on-chip ECC for low cost flash memories
Conference paper

Compact on-chip ECC for low cost flash memories

Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, …
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp.74-75
1996

Abstract

Electronic Optical and Magnetic Materials Electrical and Electronic Engineering
A compact on-chip ECC for low cost Flash memories has been developed to minimize the chip size increase. The proposed on-chip ECC implemented on a 64M NAND Flash memory has suppressed the chip size penalty to 1.9%. Moreover, the cumulative sector error rate can be improved by 4 orders after 10 6 write/erase cycles.

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