Complementary Detectors for DUV Sensing by CMOS Logic Technology

Ting-Kai Huang; Hsin-Hung Yeh; Jiaw-Ren Shih; Chrong-Jung Lin; Ya-Chin King

doi:10.1109/VLSITSA60681.2024.10546391

會議論文

Complementary Detectors for DUV Sensing by CMOS Logic Technology

Ting-Kai Huang, Hsin-Hung Yeh, Jiaw-Ren Shih, Chrong-Jung Lin 和 Ya-Chin King

2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)

IEEE

2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA) (HsinChu, Taiwan, 24/04/2024–25/04/2024)

22/04/2024

DOI: https://doi.org/10.1109/VLSITSA60681.2024.10546391

Web of Science ID: WOS:001253001400051

摘要

CMOS technology

Couplings

Detectors

Logic gates

MOSFET

MOSFET circuits

Very large scale integration

This study presents a DUV photo-detector founded upon a floating-gate-based complementary circuit unit. With a floating-gate-controlled CMOS gate, the proposed unit exhibits a widen sensing range in response to DUV dosage. Successful experimental demonstrations have elucidated the device's electrical behavior when subjected to varying durations of DUV irradiation, allowing for a timely and precise response to the dosage of DUV light.

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詳細資料

題名: Complementary Detectors for DUV Sensing by CMOS Logic Technology
創作者：: Ting-Kai Huang - 國立清華大學, 半導體研究學院
Hsin-Hung Yeh - National Tsing Hua University
Jiaw-Ren Shih - Institute of Electronics Engineering, National Tsing Hua University,Hsinchu,Taiwan
Chrong-Jung Lin - 國立清華大學, 半導體研究學院
Ya-Chin King - National Tsing Hua University
會議: 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA) (HsinChu, Taiwan, 24/04/2024–25/04/2024)
出版者: IEEE
總頁數: 2
學術資源類型: 會議論文
出版日期: 22/04/2024
出版資訊: 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
語言: 英語

Complementary Detectors for DUV Sensing by CMOS Logic Technology

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