Abstract
In complex digital systems with high operating frequencies and large chip sizes, concurrent flip-flop and buffer insertion becomes inevitable for interconnect optimization. To preserve functional integrity, the pipeline constraint must be satisfied. Moreover, blockage avoidance, power reduction, and timing margin increase are also important issues. In this paper, we study the problem of blockage-aware concurrent flip-flop and buffer insertion for latency minimization while satisfying the pipeline constraint. We also consider power dissipation or timing margin as the second objective to optimize. We present two algorithms to solve the problem, one for simultaneous minimization of latency and power dissipation and the other for simultaneous optimization of latency and timing margin. In comparison with an approach, called MiLa+GiLa [2], our algorithms are able to find a solution with the same or even smaller latency for each test case. Besides, our algorithms can reduce power by up to 9% and increase timing margin by 6X as compared to MiLa+GiLa.