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Concurrent error detection of CMOS digital and analog faults
Conference paper

Concurrent error detection of CMOS digital and analog faults

Yeong-Ruey Shieh and Cheng-Wen Wu
IEEE Xplore Digital Library European Test Conference, 1993. Proceedings of ETC 93., Third, pp.74-81
1993
DOI: https://doi.org/10.1109/ETC.1993.246531

Abstract

Fault detection;Circuit faults;Electrical fault detection;CMOS technology;Semiconductor device modeling;Circuit testing;Monitoring;Clocks;Switching circuits;Degradation
The authors present a novel approach to designing TSC (totally self-checking) CMOS circuits, considering transistor stuck-on faults. Their approach is delineated by a design-for-testability (DFT) technique, which requires a very small constant number of extra transistors, coupled with a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry can defect the faults in the functional circuit and it can detect or tolerate the faults in itself

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