Cryogenic DC and microwave characterization and modeling of 40-nm CMOS for quantum computing applications

This paper examines the experimental DC and microwave characteristics and modeling of 40-nm bulk NMOS and PMOS devices across temperatures ranging from 300 K to 4 K. DC results reveal distinct behavior at 4 K compared to room temperature, including an up to 56% increase in drain current, higher transconductance (Gm), and elevated threshold voltage (Vth). Measured S-parameters also indicate significant improvements infT (up to 40%) and fmax (~2x), and the NMOS exhibited greater variation than PMOS at cryogenic temperatures. Also, small-signal equivalent circuit model parameters are extracted to observe parameter changes with different transistor sizes as temperature reduces to 4 K. The established small-signal model shows excellent agreement with the measured results. These findings contribute valuable insights for cryogenic CMOS circuit design in quantum computing applications.