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DMP-BFP: Dynamic Mixed-Precision Block Floating-Point and Exponent-Guided Precision Adjustment
會議論文

DMP-BFP: Dynamic Mixed-Precision Block Floating-Point and Exponent-Guided Precision Adjustment

Yu-Chih Tsai, Chia-Cheng Chang 和 Ren-Shuo Liu
Proceedings - IEEE International Conference on Computer Design, 頁碼.33-40
IEEE
2025 IEEE 43rd International Conference on Computer Design (ICCD) (Richardson, TX, USA, 10/11/2025–12/11/2025)
10/11/2025
Web of Science ID: WOS:001684940200005

摘要

Accuracy block floating-point CNN dynamic mixed-precision Hardware Power demand precision adjustment process engine Quantization (signal) Runtime Sensitivity Computer Architecture Energy Efficiency Engines Software
Block Floating-Point (BFP), an emerging datatype, has demonstrated significant potential in model accuracy and hardware efficiency. This paper presents a dynamic mixedprecision BFP processing engine (PE), an accompanying framework, and optimization techniques to improve hardware efficiency. First, we propose a strategy for identifying accuracysensitive inner products within BFP models by comparing exponent values against predefined thresholds. This enables precision adjustments according to the sensitivity of the calculations at runtime. Second, we observe that only a small subset of inner products require full-precision (i.e., accuracy-sensitive inner products). Furthermore, a full-precision multiplication can be decomposed into four low-precision multiplications. Based on this, we propose the design of a low-precision PE capable of supporting full-precision mode, thereby reducing area overhead. Third, we optimize the BFP quantization scheme and datatype representation within the PE, significantly mitigating quantization errors in low-precision mode and reducing power consumption during datatype conversion. Finally, experimental results demonstrate that our dynamic mixed-precision BFP approach maintains accuracy while employing over 80% lowprecision operations and increases this ratio to 95% through retraining. Compared to state-of-the-art BFP architectures, our design improves inference speed, area efficiency, and energy efficiency by up to 1.64 ×, 1.42 × , and 1.47 × , respectively.

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