Abstract
In this paper, an all-digital differentially encoded quaternary phase shift keying (DEQPSK) direct sequence spread-spectrum (DSSS) transceiver is proposed. It consists of two parts: a baseband/IF spread-spectrum transmitter and a coherent intermediate frequency (IF) receiver. The center frequency of this IF receiver is 11 MHz and the sampling rate is 44 Msamples/second. Modulation/demodulation, carrier recovery, PN code acquisition, and differential coding are all provided within a single chip. Functional optimization and architecture design have been done before layout implementation. Furthermore, we added testing circuits in this chip and thus each functional block is easily tested. The chip was fabricated through TSMC 0.8 /spl mu/m n-well CMOS SPDM technology. The maximum operational clock rate is measured at over 90 MHz (5 V, over 4 Mbps), and the minimum supply voltage for 2 Mbps (44 MHz) rated speed is 2.6 V.