Logo image
Design and test of a scalable security processor
Conference paper

Design and test of a scalable security processor

Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang and Cheng-Wen Wu
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Vol.1, pp.372-375
2005

Abstract

Computer Science Applications Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering
This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18μm CMOS technology, The core area is 3.899mm times; 2.296mm (525K gates approximately) and the operating clock rate is 83MHz. © 2005 IEEE.

Metrics

1 Record Views

Details

Logo image