Abstract
A Dft (Design for Testability) scheme for the output buffer amplifiers of the flat-panel display signal driver is proposed. During the test mode, some of the buffers are grouped and converted to a buffer train. All buffers of signal driver are then divided to some buffer trains. The input pattern is applied to the first buffer of a buffer train. The output is measured from the last buffer of the buffer train. The tolerance bond is determined by using a Monte Carlo analysis taking into account the process variations of technology and design parameters. Faults in the buffers under test that cause an offset voltage to exit the tolerance band can therefore be detected. The number of the needed output pin of the CUT for the measurement is reduced. This test technique eliminates the need for costly high pin-count ATE (Automatic Test Equipment) and may be considered as a low-cost test scheme.