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Design of a scalable many-core processor for embedded applications
Conference paper

Design of a scalable many-core processor for embedded applications

Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu and Jing-Jia Liou
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, pp.24-25
11/03/2015

Abstract

We present a novel design of scalable many-core processor with its comprehensive development framework, including the Electronic System Level, Register Transfer Level, and full-system prototyping platforms. Architecture exploration, performance evaluation and system verification/validation can be done across different abstraction levels. With our hardware-independent software layer, applications built on top of the fast virtual platform can be executed seamlessly on the prototype. The emulation result justifies the effectiveness of our processor architecture in embedded applications. © 2015 IEEE.

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