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Design of easily testable VLSI arrays for discrete cosine transform
Conference paper

Design of easily testable VLSI arrays for discrete cosine transform

S.-K. Lu, C.-W. Wu and S.-Y. Juo
IEEE Xplore Digital Library Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference
1992
DOI: https://doi.org/10.1109/ACSSC.1992.269072

Abstract

Very large scale integration;Discrete cosine transforms;Circuit testing;Systolic arrays;Hardware;Fault detection;Circuit faults;Logic arrays;Fault diagnosis;Computer architecture
A design-for-testability approach based on the M-testability conditions is applied to the bit-level VLSI systolic arrays for discrete cosine transform (DCT), which guarantee 100% single-cell-fault testability with a minimum number of test patterns. A hardware overhead of no more than 6% is sufficient to make the DCT arrays M-testable. The resulting number of test patterns is only 16, regardless of the size of the DCT array and the internal word length. DCT array testing using the module-fault model also is discussed. M-testable arrays are proposed. An offline fault diagnosis scheme which detects and locates any faulty module in the DCT array by self-comparison is presented

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