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Diagnosis of delay defects using statistical timing models
Conference paper

Diagnosis of delay defects using statistical timing models

A. Krstic, L.-C. Wang, Kwang-Ting Cheng and Jing-Jia Liou
Proceedings of the IEEE VLSI Test Symposium, Vol.2003-January, pp.339-344
2003
DOI: https://doi.org/10.1109/VTEST.2003.1197672

Abstract

Circuit faults Circuit noise Circuit simulation Delay effects Dictionaries Fault diagnosis Logic testing Manufacturing processes Random variables Timing
In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timing information based upon single defect assumption. We evaluate its performance and its applicability to single as well as multiple defect scenarios via statistical defect injection and simulation. With a statistical timing analysis framework developed in the past, we demonstrate the new concept in statistical delay defect diagnosis, and discuss experimental results using benchmark circuits. © 2003 IEEE.

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